FIG. 1 illustrates a conventional line driver circuit which transfers a data signal from its input at the inverter 1 to the driver output without changing its polarity. The output of the inverter 1 is applied to the gate of the active FET device 4 and also to the input of the inverter 2. The output of the inverter 2 is applied to the gate of the FET load device 3. The FET active device 4 has a relatively low on-resistance R4 and the FET load device 3 has a relatively low on-resistance R3. When the conventional driver circuit of FIG. 1 is in its binary 1 state with the relatively high level binary signal at the data input and at the data output, the circuit can be inadvertently destroyed by the accidental grounding of the output terminal. This would cause excessive current to be conducted from the drain potential VDD through the relatively low resistance R3 of the load device 3 to the output node. The magnitude of the shorting current could be reduced by increasing the resistance R3 of the load device 3, however this will severely impair the rise time characteristics of the output signal during ordinary operation since the signal current passing through the load device 3 must charge the output capacitance C.sub.out in transitioning from the low level to the high level.